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DS1486/DS1486p ramified watchdog timekeeper DS1486/DS1486p preliminary 070298 1/16 features ? 128k bytes of user nv ram ? integrated nv sram, real time clock, crystal, power fail control circuit and lithium energy source ? totally nonvolatile with over 10 years of operation in the absence of power ? watchdog timer restarts an outofcontrol processor ? alarm function schedules realtime related activities such as system wakeup ? programmable interrupts and square wave output ? all registers are individually addressable via the ad- dress and data bus ? interrupt signals active in power-down mode ordering information DS1486 xxx (32pin dip module) 150 150 ns access 120 ns access 120 *DS1486p 34pin powercap module board 150 150 ns access 120 ns access 120 *ds9034pcx powercap required (must be ordered seperately) xxx pin description intb interrupt output a (open drain) intb (intb) interrupt output b (open drain) a0a16 address inputs dq0dq7 data input/output ce chip enable oe output enable we write enable v cc +5 volts gnd ground sqw square wave output nc no connection x1, x2 crystal connection v bat battery connection pin assignment dq3 dq4 dq5 dq6 dq7 a10 a11 a9 a8 v cc a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 gnd 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 a14 a13 intb (intb) we oe ce DS1486 128k x 8 32pin encapsulated package a16 a15 inta/ sqw oe ce we pfo v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 34 33 32 31 30 29 28 27 26 25 24 23 22 14 15 16 17 21 20 19 18 sqw a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a15 a16 dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 gnd 34pin powercap module board x1 gnd v bat x2 (uses ds9034pcx powercap) intb (intb) inta
DS1486p 070298 2/16 description the DS1486 is a nonvolatile static ram with a full func- tion real time clock (rtc), alarm, watchdog timer, and interval timer which are all accessible in a bytewide format. the DS1486 contains a lithium energy source and a quartz crystal which eliminates the need for any external circuitry. data contained within 128k by 8bit memory and the timekeeping registers can be read or written in the same manner as bytewide static ram. the timekeeping registers are located in the first 14 by- tes of memory space. data is maintained in the rami- fied timekeeper by intelligent control circuitry which de- tects the status of v cc and write protects memory when v cc is out of tolerance. the lithium energy source can maintain data and real time for over ten years in the ab- sence of v cc . timekeeper information includes hun- dredths of seconds, seconds, minutes, hours, day, date, month, and year. the date at the end of the month is automatically adjusted for months with less than 31 days, including correction for leap year. the ramified timekeeper operates in either 24 hour or 12 hour format with an am/pm indicator. the watchdog timer provides alarm interrupts and interval timing between 0.01 sec- onds and 99.99 seconds. the real time alarm provides for preset times of up to one week. interrupts for both watchdog and rtc will operate when system is pow- ered down. either can provide system awake-upo sig- nals. packages the DS1486 is available in two packages (32pin dip module and 34pin powercap module). the 32pin dip style module integrates the crystal, lithium energy source, and silicon all in one package. the 32pin powercap module board is designed with contacts for connection to a separate powercap (ds90934pcx) that contains the crystal and battery. the design allows the powercap to be mounted on top of the DS1486p after the completion of the surface mount process. mounting the powercap after the surface mount pro- cess prevents damage to the crystal and battery due to high temperatures required for solder reflow. the pow- ercap is keyed to prevent reverse insertion. the pow- ercap module board and powercap are ordered sepa- rately and shipped in separate containers. the part number for the powercap is ds9034pcx. operation read registers the DS1486 executes a read cycle whenever we (write enable) is inactive (high), ce (chip enable) and oe (output enable) are active (low). the unique ad- dress specified by the address inputs (a0a16) defines which of the registers is to be accessed. valid data will be available to the eight data output drivers within t acc (access time) after the last address input signal is stable, providing that ce and oe access times are also satisfied. if oe and ce access times are not satisfied, then data access must be measured from the latter oc- curring signal (ce or oe ) and the limiting parameter is either t co for ce or t oe for oe rather than address ac- cess. operation write registers the DS1486 is in the write mode whenever the we (write enable) and ce (chip enable) signals are in the active (low) state after the address inputs are stable. the latter occurring falling edge of ce or we will deter- mine the start of the write cycle. the write cycle is termi- nated by the earlier rising edge of ce or we . all address inputs must be kept valid throughout the write cycle. we must return to the high state for a minimum recovery state (t wr ) before another cycle can be initiated. data must be valid on the data bus with sufficient data set-up (t ds ) and data hold time (t dh ) with respect to the earlier rising edge of ce or we . the oe control signal should be kept inactive (high) during write cycles to avoid bus contention. however, if the output bus has been en- abled (ce and oe active), then we will disable the out- puts in t odw from its falling edge. data retention the ramified timekeeper provides full functional capa- bility when v cc is greater than 4.5 volts and writepro- tects the register contents at 4.25 volts typical. data is maintained in the absence of v cc without any additional support circuitry. the DS1486 constantly monitors v cc . should the supply voltage decay, the ramified time- keeper will automatically write-protect itself and all in- puts to the registers become adon't careo. the two inter- rupts inta and intb (intb) and the internal clock and timers continue to run regardless of the level of v cc . however, it is important to insure that the pullup resis- tors used with the interrupt pins are never pulled up to a value that is greater than v cc + 0.3v. as v cc falls below approximately 3.0 volts, a power switching circuit turns the internal lithium energy source on to maintain the clock and timer data functionality. it is also required to insure that during this time (battery backup mode), the voltage present at inta and intb (intb) does never
DS1486p 070298 3/16 exceed vbat. during power-up, when v cc rises above approximately 3.0 volts, the power switching circuit con- nects external v cc and disconnects the internal lithium energy source. normal operation can resume after v cc exceeds 4.5 volts for a period of 200 ms. ramified timekeeper registers the ramified timekeeper has 14 registers which are eight bits wide that contain all of the timekeeping, alarm, watchdog and control information. the clock, calendar, alarm, and watchdog registers are memory locations which contain external (useraccessible) and internal copies of the data. the external copies are independent of internal functions except that they are updated peri- odically by the simultaneous transfer of the incremented internal copy (see figure 1). the command register bits are affected by both internal and external functions. this register will be discussed later. registers 0, 1, 2, 4, 6, 8, 9, and a contain time of day and date information (see figure 2). time of day information is stored in bcd. registers 3, 5, and 7 contain the time of day alarm in- formation. time of day alarm information is stored in bcd. register b is the command register and infor- mation in this register is binary. registers c and d are the watchdog alarm registers and information which is stored in these two registers is in bcd. register e through 1ffff are user bytes and can be used to main- tain data at the user's discretion. clock accuracy (dip module) the DS1486 is guaranteed to keep time accuracy to within 1 minute per month at 25 c. clock accuracy (powercap module) the DS1486p and ds9034pcx are each individually tested fore accuracy. once mounted together, the mod- ule is guaranteed to keep time accuracy to within 1.53 minutes per month (35 ppm) at 25 c.
DS1486p 070298 4/16 block diagram figure 1 command register update seconds thru years and check time of day alarm external registers, clock, calendar, time of day alarm user ram 128k x 8 internal counters internal counters external registers watchdog alarm external registers hundredths of seconds divide by 4 swap pins power switch pf delay divide by 10 divide by 40.96 divide by 40.96 divide by 8 oscillator address decode adn countrol data i/0 buffers jitter generator oscillator & prescaler quartz crystal dq0-dq7 4096hz 32.788hz jitter generator (vbat) v cc 1024hz sqw (x1) (x2) 100hz 100hz aavgo a0-a16 ce oe we inta intb(intb) td int wd int aavgo internal registers
DS1486p 070298 5/16 time of day registers registers 0, 1, 2, 4, 6, 8, 9, and a contain time of day data in bcd. ten bits within these eight registers are not used and will always read zero regardless of how they are written. bits 6 and 7 in the months register (9) are binary bits. when set to logic zero, eosc (bit 7) en- ables the real time clock oscillator. this bit is set to logic one as shipped from dallas semiconductor to prevent lithium energy consumption during storage and ship- ment (dip module only). this bit will normally be turned on by the user during device initialization. however, the oscillator can be turned on and off as necessary by set- ting this bit to the appropriate level. the inta and square wave output signals are tied together at pin 30 on the 32pin dip module. with this package, bit 6 of the months register (9) controls the function of this pin. when set to logic zero, the pin will output a 1024 hz square wave signal. when set to logic one, the pin is available for interrupt a output (inta ) only. the inta and square wave output signals are separated on the 34pin powercap module. with this package, bit 6 of the months register (9) controls only the square wave output (pin 33). when set to logic zeros, pin 33 will out- put a 1024 hz square wave signal. when set to logic one, pin 33 is in a high impedance state. pin 34 (inta ) is not affected by the setting of bit 6. bit 6 of the hours reg- ister is defined as the 12 or 24 hour select bit. when set to logic one, the 12 hour format is selected. in the 12 hour format, bit 5 is the am/pm bit with logic one being pm. in the 24 hour mode, bit 5 is the second 10 hour bit (2023 hours). the time of day registers are updated every 0.01 seconds from the real time clock, except when the te bit (bit 7 of register b) is set low or the clock oscillator is not running. the preferred method of synchronizing data access to and from the ramified timekeeper is to access the command register by do- ing a write cycle to address location 0b and setting the te bit (transfer enable bit) to a logic zero. this will freeze the external time of day registers at the present recorded time, allowing access to occur without danger of simultaneous update. when the watch registers have been read or written, a second write cycle to location 0b, setting the te bit to a logic one, will put the time of day registers back to being updated every 0.01 sec- ond. no time is lost in the real time clock because the internal copy of the time of day register buffers is con- tinually incremented while the external memory regis- ters are frozen. an alternate method of reading and writ- ing the time of day registers is to ignore synchronization. however, any single read may give er- roneous data as the real time clock may be in the pro- cess of updating the external memory registers as data is being read. the internal copies of seconds through years are incremented, and the time of day alarm is checked during the period that hundreds of seconds reads 99 and are transferred to the external register when hundredths of seconds roll from 99 to 00. a way of making sure data is valid is to do multiple reads and compare. writing the registers can also produce erro- neous results for the same reasons. a way of making sure that the write cycle has caused proper update is to do read verifies and reexecute the write cycle if data is not correct. while the possibility of erroneous results from reads and write cycles has been stated, it is worth noting that the probability of an incorrect result is kept to a minimum due to the redundant structure of the rami- fied timekeeper. time of day alarm registers registers 3, 5, and 7 contain the time of day alarm registers. bits 3, 4, 5, and 6 of register 7 will always read zero regardless of how they are written. bit 7 of registers 3, 5, and 7 are mask bits (figure 3). when all of the mask bits are logic zero, a time of day alarm will only occur when registers 2, 4, and 6 match the values stored in registers 3, 5, and 7. an alarm will be gener- ated every day when bit 7 of register 7 is set to a logic one. similarly, an alarm is generated every hour when bit 7 of registers 7 and 5 is set to a logic 1. when bit 7 of registers 7, 5, and 3 is set to a logic 1, an alarm will occur every minute when register 1 (seconds) rolls from 59 to 00. time of day alarm registers are written and read in the same format as the time of day registers. the time of day alarm flag and interrupt are always cleared when alarm registers are read or written. watchdog alarm registers registers c and d contain the time for the watchdog alarm. the two registers contain a time count from 00.01 to 99.99 seconds in bcd. the value written into the watchdog alarm registers can be written or read in any order. any access to register c or d will cause the watchdog alarm to reinitialize and clears the watchdog flag bit and the watchdog interrupt output. when a new value is entered or the watchdog registers are read, the watchdog timer will start counting down from the entered value to zero. when zero is reached, the watchdog interrupt output will go to the active state. the watchdog timer countdown is interrupted and re-
DS1486p 070298 6/16 initialized back to the entered value every time either of the registers are accessed. in this manner, controlled periodic accesses to the watchdog timer can prevent the watchdog alarm from going to an active level. if ac- cess does not occur, countdown alarm will be repetitive. the watchdog alarm registers always read the en- tered value. the actual count- down register is internal and is not readable. writing registers c and d to zero will disable the watchdog alarm feature. DS1486 ramified timekeeper registers figure 2 0 1 2 3 4 5 6 7 8 9 a b c d e address bit 7 bit 0 range 0.1 seconds 0.01 seconds 10 seconds seconds 10 minutes min alarm 12/24 hr alarm days day alarm 10 date date 10mo months 10 years years te ipsw ibh lo pu lvl wam tdm waf tdf 0099 0059 0112+a/p 0023 0107 0131 0112 clock, calendar, time of day alarm registers command registers watchdog alarm registers user registers 0 0 minutes 10 min alarm 10 a/p hours m 12/24 10 a/p 00 00 0 0 00 0 0.1 seconds 0.01 seconds 10 seconds seconds 0 0 0059 0059 0099 0112+a/p 0023 0107 0099 0099 0 hr hr eosc esqw 0 10 10 m m 1ffff
DS1486p 070298 7/16 time of day alarm mask bits figure 3 (3) minutes (5) hours (7) days 1 0 alarm once per minute alarm when minutes match alarm when hours and minutes match alarm when hours, minutes, and days match 11 1 1 1 0 0 00 0 note: any other bit combinations of mask bit settings produce illogical operation. register command register address location 0bh is the command register where mask bits, control bits and flag bits reside. the opera- tion of each bit is as follows: te bit 7 transfer enable this bit when set to a logic 0 will disable the transfer of data between internal and ex- ternal clock registers. the contents in the external clock registers are now frozen and reads or writes will not be affected with updates. this bit must be set to a logic 1 to allow updates. ipsw bit 6 interrupt switch when set to a logic 1, inta is the time of day alarm and intb/(intb ) is the watchdog alarm. when set to logic 0, this bit reverses the output pins. inta is now the watchdog alarm output and intb/(intb ) is the time of day alarm output. the inta /sqw output pin shares both the interrupt a and square wave output function. inta and the square wave function should never be simultaneously enabled or a conflict may occur. (32pin dip module only). ibh/lo bit 5 interrupt b sink or source current when this bit is set to a logic 1 and v cc is applied, intb/(intb ) will source current (see dc characteristics ioh). when this bit is set to a logic 0, intb will sink cur- rent (see dc characteristics iol). pu/lvl bit 4 interrupt pulse mode or level mode this bit determines whether both interrupts will output a pulse or level signal. when set to a logic 0, inta and intb/(intb ) will be in the level mode. when this bit is set to a logic 1, the pulse mode is selected and inta will sink current for a minimum of 3 ms and then release. intb/(intb ) will either sink or source current, depend- ing on the condition of bit 5, for a minimum of 3 ms and then release. intb will only source current when there is a voltage present on v cc . wam bit 3 watchdog alarm mask when this bit is set to a logic 0, the watchdog interrupt output will be acti- vated. the activated state is determined by bits 1,4,5, and 6 of the command register. when this bit is set to a logic 1, the watchdog interrupt output is deacti- vated. tdm bit 2 time of day alarm mask when this bit is set to a logic 0, the time of day alarm interrupt output will be activated. the activated state is determined by bits 0, 4, 5, and 6 of the command register. when this bit is set to a logic 1 , the time of day alarm interrupt output is deactivated. waf bit 1 watchdog alarm flag this bit is set to a logic 1 when a watchdog alarm interrupt occurs. this bit is read only. the bit is reset when any of the watchdog alarm regis- ters are accessed. when the interrupt is in the pulse mode (see bit 4 defini- tion), this flag will be in the logic 1 state only during the time the interrupt is active. tdf bit 0 time of day flag this is a read only bit. this bit is set to a logic 1 when a time of day alarm has occurred. the time the alarm occurred can be deter- mined by reading the time of day alarm registers. this bit is reset to a logic 0 state when any of the time of day alarm registers are accessed. when the interrupt is in the pulse mode (see bit 4 defini- tion), this flag will be in the logic 1 state only during the time the interrupt is active.
DS1486p 070298 8/16 absolute maximum ratings* voltage on any pin relative to ground 0.3v to +7.0v operating temperature 0 c to 70 c storage temperature 40 c to + 70 c soldering temperature 260 c for 10 seconds (see note 14) * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (0 c to 70 c) parameter symbol min typ max units notes supply voltage v cc 4.5 5.0 5.5 v 10 input logic 1 v ih 2.2 v cc + 0.3 v 10 input logic 0 v il 0.3 +0.8 v 10 dc electrical characteristics (0 c to 70 c; v cc = 5v + 10%) parameter symbol min typ max units notes input leakage current i il 1.0 +1.0 m a output leakage current i lo 1.0 +1.0 m a i/o leakage current i lio 1.0 +1.0 m a output current @ 2.4v i oh 1.0 ma 13 output current @ 0.4v i ol 2.1 ma 13 standby current ce = 2.2v i ccs1 3.0 7.0 ma standby current ce = v cc 0.5 i ccs2 4.0 ma active current i cc 85 ma write protection voltage v tp 4.0 4.25 4.5 v capacitance (t a = 25 c) parameter symbol min typ max units notes input capacitance c in 7 15 pf output capacitance c out 7 15 pf input/output capacitance c i/o 7 15 pf
DS1486p 070298 9/16 ac electrical characteristics (0 c to 70 c; v cc = 5.0v + 10%) parameter symbol DS1486120 DS1486150 units notes parameter symbol min max min max units notes read cycle time t rc 120 150 ns 1 address access time t acc 120 150 ns ce access time t co 120 150 ns oe access time t oe 100 120 ns oe or ce to output active t coe 10 10 ns output high z from deselect t od 40 50 ns output hold from address change t oh 10 10 ns write cycle time t wc 120 150 ns write pulse width t wp 110 140 ns 3 address setup time t aw 0 0 ns write recovery time t wr 10 15 ns output high z from we t odw 40 50 ns output active from we t oew 10 10 ns data setup time t ds 85 110 ns 4 data hold time t dh 10 15 ns 4,5 inta , intb pulse width t ipw 3 3 ms 11,12
DS1486p 070298 10/16 read cycle (note1) addresses ce oe d out we addresses ce d out d in we addresses ce d out d in t rc v ih v il t od v oh v ol t aw t acc v ih v il v ih v il t oh t co v ih v ih t od v oh v ol t oe v ih t coe v il output data valid v ih t wc v il v ih t aw v il v ih v il v ih v il t wr t wp v ih v il v il t oew t odw high impedance t ds t dh v ih v il v ih v il data in stable t wc v il v ih t aw v ih v il v il t wp v il v ih v il v ih v ih t wr v il v ih v ih t odw t coe t ds t dh v ih v il v ih v il data in stable v il write cycle 1 (notes 2, 6, 7) write cycle 2 (notes 2, 8)
DS1486p 070298 11/16 timing diagram: interrupt outputs pulse mode (see notes 11,12) intb inta , intb t ipw powerdown/powerup timing v cc t pf t fb ce data retention t dr i batt t f 4.5v 4.0v t rec t r 4.0v v bat v bat pfo 4.5v 4.25v 4.25v
DS1486p 070298 12/16 ac electrical characteristics powerup powerdown timing (0 c to 70 c) parameter symbol min max units notes ce high to power fail t pf 0 ns recovery at power up t rec 200 ms v cc slew rate power down t f 4.0< v cc < 4.5v 300 m s v cc slew rate power down t fb 3.0< v cc < 4.25v 10 m s v cc slew rate power up t r 4.5v> v cc > 4.0v 0 m s expected data retention t dr 10 years 9 warning: under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery backup mode. notes: 1. we is high for a read cycle. 2. oe = v ih or v il . if oe = v ih during write cycle, the output buffers remain in a high impedance state. 3. t wp is specified as the logical and of the ce and we . t wp is measured from the latter of ce or we going low to the earlier of ce or we going high. 4. t ds or t dh are measured from the earlier of ce or we going high. 5. t dh is measured from we going high. if ce is used to terminate the write cycle, then t dh = 20 ns for 120 parts and t dh = 25 ns for 150 parts. 6. if the ce low transition occurs simultaneously with or later than the we low transition in write cycle 1, the output buffers remain in a high impedance state during this period. 7. if the ce high transition occurs prior to or simultaneously with the we high transition, the output buffers remain in a high impedance state during this period. 8. if we is low or the we low transition occurs prior to or simultaneously with the ce low transition, the output buffers remain in a high impedance state during this period. 9. each DS1486 is marked with a four digit date code aabb. aa designates the year of manufacture. bb designates the week of manufacture. the expected t dr is defined for dip modules as starting at the date of manufacture. 10. all voltages are referenced to ground. 11. applies to both interrupt pins when the alarms are set to pulse. 12. interrupt output occurs within 100 ns on the alarm condition existing. 13. both inta and intb (intb) are open drain outputs. 14. realtime clock modules (dip) can be successfully processed through conventional wavesoldering tech- niques as long as temperature exposure to the lithium energy source contained within does not exceed +85 c. post solder cleaning with water washing techniques is acceptable, provided that ultrasonic vibration is not used. in addition, for the powercap version: a. dallas semiconductor recommends that powercap module bases experience one pass through solder reflow oriented with the label side up (alive bugo). b. hand soldering and touch up: do not touch or apply the soldering iron to leads for more than 3 (three) seconds. to solder, apply flux to the pad, heat the lead frame pad and apply solder. to remove the part, apply flux, heat the lead frame pad until the solder reflows and use a solder wick to remove solder.
DS1486p 070298 13/16 ac test conditions input levels: 0v to 3v transition times: 5 ns ac test conditions output load: 50 pf + 1ttl gate input pulse levels: 03.0v timing measurement reference levels input: 1.5v output: 1.5v input pulse rise and fall times: 5 ns. DS1486 32pin 740 mil module a 1 dim min max a in. mm b in. mm c in. mm d in. mm e in. mm f in. mm g in. mm h in. mm j in. mm k in. mm 1.720 43.69 1.740 44.20 0.720 18.29 0.740 18.80 0.395 10.03 0.415 10.54 0.090 2.29 0.120 3.05 0.017 0.43 0.030 0.76 0.120 3.05 0.160 4.06 0.090 2.29 0.110 2.79 0.590 14.99 0.630 16.00 0.008 0.20 0.012 0.30 0.015 0.38 0.021 0.53 c f g k d h b e j 32pin pkg
DS1486p 070298 14/16 DS1486p dim min nom a 0.920 0.925 b 0.980 0.985 c d 0.052 0.055 e 0.048 0.050 f 0.015 0.020 g 0.025 0.027 pkg inches max 0.930 0.990 0.080 0.058 0.052 0.025 0.030 top view side view bottom view note: for the powercap version: a. dallas semiconductor recommends that powercap module bases experience one pass though solder reflow oriented with the label side up (alive bugo). b. hand soldering and touch up: do not touch or apply the soldering iron to leads for more than 3 (three) seconds. to solder, apply flux to the pad, heat the lead frame pad and apply solder. to remove the part, apply flux, heat the lead frame pad until the solder reflows and use a solder wick to remove solder.
DS1486p 070298 15/16 DS1486p with ds9034pcx attached dim min nom a 0.920 0.925 b 0.955 0.960 c 0.240 0.245 d 0.052 0.055 e 0.048 0.050 f 0.015 0.020 g 0.020 0.025 pkg inches max 0.930 0.965 0.250 0.058 0.052 0.025 0.030 top view side view bottom view
DS1486p 070298 16/16 recommended powercap module land pattern pkg dim inches min nom max a 1.050 b 0.826 c 0.050 d 0.030 e 0.112 a d b c e 16 pl

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